1. Field of the Invention
The present invention relates to an operational amplifier suitable for an output buffer amplifier for an LCD (Liquid Crystal Display) driver used to drive a capacitive load such as a liquid crystal panel, and for a gradation power source circuit adapted to determine gamma correction. The present invention also relates to a display device using the operational amplifier.
2. Description of the Related Art
Conventionally, a so-called operational amplifier is generally constituted by bipolar transistors. In recent years, however, the operational amplifier has also been constituted by MOS transistors in more cases according to the need to be provided together with a MOS circuit and the request for low power. In order to constitute the operational amplifier by MOS transistors, a circuit constitution different from the operational amplifier constituted by bipolar transistors may be adopted by using analog characteristics particular to the MOS transistor. For example, there is an amplifier using an electronic switch function, and the like.
As one of the application fields of the operational amplifier constituted by MOS transistors, there is a TFT_LCD (Thin Film Transistor Liquid Crystal Display) driver LSI. The LCD driver LSI includes a plurality of operational amplifiers of voltage follower constitution as an output buffer amplifier and a gradation power source for gamma correction, and particularly needs to have a small offset voltage difference between the plurality of operational amplifiers. This is because even a voltage difference of 10 mV is recognized as a different gradation by the human eye due to the characteristics of the TFT_LCD. Thus, a MOS operational amplifier having a very small offset voltage is required in this field.
FIG. 6 and FIG. 7 are circuit diagrams showing an operational amplifier applied to drive a conventional video display device (see, for example, Japanese Patent Laid-Open No. 11-249623). As shown in FIG. 6, the conventional operational amplifier is constituted by two P-channel MOS transistors MP101 and MP102, constant current sources I101, I102, N-channel MOS transistors MN101, MN102 and MN103, a phase compensation capacitance C101, and switches S101 to S108.
The two P channel MOS transistors MP101 and MP102 constitute a differential pair. The constant current source I101 biases the differential pair and is inserted between the commonly connected sources of the P channel MOS transistors MP101 and MP102, and a positive power source VDD. The N-channel MOS transistors MN101 and MN102 serve as active loads and constitute a current mirror which converts differential signals to a single output. The N-channel MOS transistor MN103 constitutes a second stage amplifier circuit. The constant current source I102 operates as an active load of the N-channel MOS transistor MN103, and is inserted between the positive power source VDD and the drain of the N-channel MOS transistor MN103. The phase compensation capacitance C101 is inserted between the gate and drain of the N-channel MOS transistor MN103.
Further, the switch S101 is a break type switch inserted between the gate and drain of the N-channel MOS transistor MN101. The switch S102 is a make type switch inserted between the gate and drain of the N-channel MOS transistor MN102. Here, the break type switch means a switch which opens (turns off) when a control signal is input. Further, the make type switch means a switch which closes (turns on) when a control signal is input.
The switch S103 is a make type switch connected between the drain of the N-channel MOS transistor MN101 and the gate of the N-channel MOS transistor MN103. The switch S104 is a break type switch connected between the drain of the N-channel MOS transistor MN102 and the gate of the N-channel MOS transistor MN103. The switch S105 is a make type switch connected between the gate of the P-channel MOS transistor MP102 and an output terminal Vout. The switch S106 is a break type switch connected between the gate of the P-channel MOS transistor MP101 and the output terminal Vout. The switch S107 is a make type switch connected between the gate of the P-channel MOS transistor MP101 and a noninverting input terminal Vin. The switch S108 is a break type switch connected between the gate of the P-channel MOS transistor MP102 and the noninverting input terminal Vin.
The drain of the P-channel MOS transistor MP101 which is one of the P-channel MOS transistors constituting the differential pair is connected to the drain of the N-channel MOS transistor MN101, while the drain of the P-channel MOS transistor MP102 which is the other of the P-channel MOS transistors constituting the differential pair is connected to the drain of the N-channel MOS transistor MN102. Then, all the switches S101 to S108 are controlled in linkage with each other. Further, as will be described below, the amplifier in FIG. 6 is used in an odd frame, and is characterized in that the switches are switched in 4n−1 frame and 4n−3 frame where n is a natural number starting from 1. The state of the switches at the time of 4n−1 frame is shown in the right figure in FIG. 6, and the state of the switches at the time of 4n−3 frame is shown in the left figure in FIG. 6.
Further, as shown in FIG. 7, another conventional operational amplifier is constituted by two N-channel MOS transistors MN201, MN202, a constant current sources I201, P-channel MOS transistors MP201, MP202 and NP203, a constant current sources I202, a phase compensation capacitance C201, and switches S201 to S208.
The two N-channel MOS transistors MN201 and MN202 constitute a differential pair. The constant current source I201 biases the differential pair, and is inserted between the commonly connected sources of the N-channel MOS transistors MN201 and MN202 and a negative power source VSS. The P-channel MOS transistors MP201 and MP202 serve as active loads and constitute a current mirror which converts differential signals to a single output. The P-channel MOS transistor NP203 constitutes a second stage amplifier circuit. The constant current source I202 operates as an active load of the P-channel MOS transistor MP203, and is inserted between the negative power source VSS and the drain of the P-channel MOS transistor MP203. The phase compensation capacitance C201 is inserted between the gate and drain of the P-channel MOS transistor MP203.
Further, the switch S201 is a break type switch inserted between the gate and drain of the P-channel MOS transistor MP201. The switch S202 is a make type switch inserted between the gate and drain of the P-channel MOS transistor MP202. The switch S203 is a make type switch connected between the drain of the P-channel MOS transistor MP201 and the gate of the P-channel MOS transistor MP203. The switch S204 is a break type switch connected between the drain of the P-channel MOS transistor MP202 and the gate of the P-channel MOS transistor MP203. The switch S205 is a break type switch connected between the gate of the N-channel MOS transistor MN202 and an output terminal Vout. The switch S206 is a break type switch connected between the gate of the N-channel MOS transistor MN201 and the output terminal Vout. The switch S207 is a break type switch connected between the gate of the N-channel MOS transistor MN201 and a noninverting input terminal Vin. The switch S208 is a make type switch connected between the gate of the N-channel MOS transistor MN202 and the noninverting input terminal Vin.
Then, the drain of the N-channel MOS transistor MN201 which is one of the N-channel MOS transistors constituting the differential pair is connected to the drain of the P-channel MOS transistor MP201. The drain of the N-channel MOS transistor MN202 which is the other of the N-channel MOS transistors constituting the differential pair is connected to the drain of the P-channel MOS transistor MP202. Then, all the switches S201 to S208 are controlled in linkage with each other. Further, as will be described below, the amplifier in FIG. 7 is used in an even frame, and is characterized in that the switches are switched in 4n−2 frame and 4n frame where n is a natural number starting from 1. The state of the switches at the time of 4n frame is shown in the right figure in FIG. 7, and the state of the switches at the time of 4n−2 frame is shown in the left figure in FIG. 7.
Next, there is shown in FIG. 8 an application example in the case where the amplifiers shown in FIG. 6 and FIG. 7 are applied to an LCD driver. As shown in FIG. 8, the amplifier shown in FIG. 7 is applied to an AMP101, and the amplifier shown in FIG. 6 is applied to an AMP102. Then, the transfer type switches (SW101 and SW102) are respectively provided for the outputs of the amplifiers AMP101 and AMP102. The outputs of the amplifier AMP101 and the amplifier AMP102 are switched for an odd-numbered (Vout odd) output and an even-numbered (Vout even) output, respectively. When a certain state is taken at this time, the output of the amplifier AMP101 is output at the odd-numbered order, and the output of amplifier AMP102 is output at the even-numbered order. Another state is opposite to the certain state. At this time, the output of the amplifier AMP101 is output at the even-numbered order, and the output of amplifier AMP102 is output at the odd-numbered order. Then, positive side data are input to the input of the amplifier AMP101, and negative side data are input to the input of the amplifier AMP102. When the switches SW101 and SW102 connected in this manner are operated in linkage with each other for each frame, an output image as shown in the right figure in FIG. 8 is obtained. Note that in a driving system referred to as dot inversion driving, the SW101 and SW102 are switched for each horizontal period. Here, the detailed description of the driving system is omitted.
Next, an operation of the conventional operational amplifier will be described. The conventional operational amplifier shown in FIG. 6 includes the P-channel MOS transistors MP101 and MP102 constituting the differential pair, and the N-channel MOS transistors MN101 and MN102 of a current mirror constitution which serve as an active load of the differential pair and have a differential to single-end conversion function. Here, when the switch S101 is closed, the drain of the N-channel MOS transistor MN102 serves as a single end output, and when the switch S102 is closed, the drain of N-channel MOS transistor MN101 serves as a single end output.
The output terminal is changed by the states of the switch S101 and the switch S102 in this way, and hence the switch S103 and the switch S104 are provided for the selection of the outputs. A signal subjected to the single conversion is inputted into the gate of the N-channel MOS transistor MN103 constituting the output transistor, through the switch S103 and the switch S104. At this time, the constant current source I102 operates as an active load of the N-channel MOS transistor MN103. Then, the drain of the N-channel MOS transistor MN103 serves as the output terminal Vout.
The capacitance C101 performs a function of phase compensation as a mirror capacity. The operational amplifier is subjected to so-called voltage follower connection in which an inverting input terminal and the output terminal Vout are commonly connected, in order to be used as a buffer amplifier. The voltage follower connection is a system in which the inverting input terminal and the output terminal of the AMP are connected in common, an input signal is input into the noninverting input terminal, and an output having the same voltage as the input voltage is output from the output terminal of the AMP.
When the switches S101 to S104 are switched, the gate of the P-channel MOS transistor MP101 or the gate of the P-channel MOS transistor MP102 can be used as the inverting input terminal. Therefore, the switch S105 and the switch S106 are provided in order to switch the input terminal. That is, as shown in the left figure in FIG. 6, when the switch S101 and the switch S104 are closed, the gate terminal of the P-channel MOS transistor MP101 is used as the inverting input terminal. Therefore, when the switch S106 is closed at this time, the inverting input terminal and the output terminal Vout are connected in common so as to effect the voltage-follower connection. Thus, the gate terminal of the P-channel MOS transistor MP102 serves as the noninverting input terminal Vin, and hence is connected to the noninverting input terminal Vin by closing the switch S108.
On the contrary, as shown in the right figure in FIG. 6, when the switch S102 and the switch S103 are closed, the gate terminal of the P-channel MOS transistor MP102 serves as the inverting input terminal. Therefore, when the switch S105 is closed at this time, the inverting input terminal and the output terminal Vout are connected in common, so as to effect voltage-follower connection. The gate terminal of the P-chain channel MOS transistor MP101 serves as the noninverting input terminal Vin, and hence is connected to the noninverting input terminal Vin by closing the switch S107. The two states are made to exist by the switching of the switches S101 to S108. The two states are switched by the 4n−3 frame and the 4n−1 frame, as described above. Assuming that an offset voltage +Vos is generated in the conventional operational amplifier shown in FIG. 6, when the switches S101 to S108 are switched, the offset voltage becomes −Vos at this time. Thus, the offset is spatially scattered by switching the switches S101 to S108 at the 4n−3 frame and the 4n−1 frame, so that the offset voltage becomes zero when averaged. Therefore, the offset voltage is recognized as the averaged voltage, that is, zero by the human eye. In other words, this system is a technique of deceiving the human eye.
The amplifier shown in FIG. 6 has a differential stage constituted by the P-channel, and hence a voltage greater than or equal to about VDD−1V cannot be input as the input at the side of the positive power source VDD. This is because the bias current source I101 is made to be inoperative by the gate-source voltage of the P-channel MOS transistors MP101 and MP102 of the differential stage. However, depending upon the gate-source voltage of the N-channel MOS transistors MN101 and MN102 as the active load, a voltage up to almost VSS can be input in a range close to VSS.
The conventional operational amplifier shown in FIG. 7 includes the N-channel MOS transistors MN201 and MN202 constituting the differential pair, and the P-channel MOS transistors MP201 and MP202 of a current mirror constitution which serve as an active load and have a differential to single end conversion function. Here, when the switch S201 is closed, the drain of the P-channel MOS transistor MP202 serves as a single end output, while when the switch S102 is closed, the drain of the P-channel MOS transistor MP201 serves as a single end output.
Since the output terminal is changed by the states of the switch S201 and the switch S202, the switch 5203 and the switch S204 are provided for the selection of the outputs. A signal subjected to the single conversion is input into the gate of the P-channel MOS transistor MP203 serving as the output transistor, through the switch S203 and the switch S204. At this time, the constant current source I202 operates as an active load of the P-channel MOS transistor MP203. Thus, the drain of the P-channel MOS transistor MP203 serves as the output terminal Vout. The capacitance C201 performs a function of phase compensation as a mirror capacity. The operational amplifier is subjected to so-called voltage follower connection in which an inverting input terminal and the output terminal Vout are commonly connected, in order to be used as a buffer amplifier.
Here, when the switches S201 to S204 are switched, the gate of the N-channel MOS transistor MN201 or the gate of the N-channel MOS transistor MN202 serves as the inverting input terminal. Therefore, the switch S205 and the switch S206 are provided in order to switch the gates of the N-channel MOS transistors. That is, as shown in the left figure in FIG. 7, when the switch S201 and the switch S204 are closed, the gate terminal of the N-channel MOS transistor MN201 serves as the inverting input terminal. Therefore, when the switch S206 is closed at this time, the inverting input terminal and the output terminal Vout are connected in common so as to effect the voltage-follower connection.
Thus, the gate terminal of the N-channel MOS transistor MN202 serves as the noninverting input terminal Vin, and hence is connected to the noninverting input terminal Vin by closing the switch S208. On the contrary, as shown in the right figure in FIG. 7, when the switch S202 and the switch S203 are closed, the gate terminal of the N-channel MOS transistor MN202 serves as the inverting input terminal. Therefore, when the switch S205 is closed at this time, the inverting input terminal and the output terminal Vout are connected in common so as to effect the voltage-follower connection. Thus, the gate terminal of the N-channel MOS transistor MN201 serves as the noninverting input terminal Vin, and hence is connected to the noninverting input terminal Vin by closing the switch S207. The two states are made to exist by the switching of the switches S201 to S208. The two states are switched by 4n−2 frame and 4n frame, as described above. Assuming that an offset voltage +Vos is generated in the conventional operational amplifier shown in FIG. 7, when the switches S201 to S208 are switched, the offset voltage becomes −Vos at this time.
Similarly to the case shown in FIG. 6, the offset is spatially scattered by switching the switches S201 to S208 by 4n−2 frame and 4n frame, so that the offset voltage becomes zero when averaged. Therefore, the offset voltage is recognized as the averaged voltage, that is, zero by the human eye.
The operational amplifier shown in FIG. 7 has a differential stage constituted by the N-channel, and hence a voltage less than or equal to about VSS+1 V cannot be input as the input at the side of the negative power source. This is because the bias current source 1201 is made to be inoperative by the gate-source voltage of the MOS transistors MN201 and MN202 of the differential stage. However, depending upon the gate-source voltage of the P-channel MOS transistors MP201 and MP202 as the active load, a voltage up to almost VDD can be input in a range close to VDD.
FIG. 8 shows an application example in the case where the operational amplifier shown in FIG. 7 is used as the positive side (VDD/2 to VDD) amplifier of an LCD driver, and the operational amplifier shown in FIG. 6 is used as the negative side (VSS to VDD/2) amplifier of the LCD driver. As shown in FIG. 8(A), in the amplifier AMP101, the operational amplifier shown in FIG. 7 is used as the amplifier dedicated for the positive side, while in the amplifier AMP102, the operational amplifier shown in FIG. 6 is used as the amplifier dedicated for the negative side. Then, each of the amplifiers is provided with a switching output so as to be able to output each of an odd-numbered output (Vout_odd) and an even-numbered output (Vout_even). This makes it possible to output both voltages of a positive side voltage and a negative side voltage for each of the odd-numbered output and the even-numbered output. This is the so-called conventional two AMP system.
Here, the driving method of LCD driver referred to as dot inversion driving is a driving method configured to alternately output the positive side (+) polarity and the negative side (−) polarity for each dot on the basis of VCOM. Further, it is necessary to invert the polarity for each frame. Therefore, in order to perform the offset cancellation on the basis of the frame signal, the driving method is configured to use four frames as one set, as shown in FIG. 8(B). That is, when the positive side (+) polarity is output by the amplifier AMP101 in the first frame, the negative side (−) polarity is output by the amplifier AMP102 in the second frame. At this time, it is assumed that the offset cancellation signal is not changed in the first frame and the second frame.
Then, in the third frame, the offset cancellation signal is inverted and the positive side (+) polarity is made to be output by the amplifier AMP101. In the fourth frame, the offset cancellation signal is made to remain in the inverted state and the negative side (−) polarity is made to be output by the amplifier AMP102. Here, the image quality is influenced by the sum of absolute values of the positive side (+) amplitude and the negative side (−) amplitude. When the differences in the amplitude A and the amplitude B shown in FIG. 7(B) are the same, the images are recognized to have the same gradation. Therefore, when the absolute values of the offset voltage based on the offset cancellation control signal are the same in each of the positive side and the negative side before and after the control of the offset cancellation control signal, the amplitude A and the amplitude B consequently become the same value. In this way the offset cancellation can be effected. Here, the difference between the amplitude A and the amplitude B is referred to as an amplitude difference deviation. The amplitude difference deviation is a most important item in the LCD driver. If the amplitude difference deviation is large, there arise a problem that vertical stripes are caused in the LCD display.
However, when the LCD driver shown in FIG. 8 is constituted by making the operational amplifier shown in FIG. 6 dedicated for the negative side and making the operational amplifier shown in FIG. 7 dedicated for the positive side, the positive side and the negative side are constituted by separate operational amplifiers, which naturally results in different offset voltages in the positive side and the negative side. Further, even when the offset cancellation is applied, the offset voltage cannot be made to zero. Therefore, offset voltage differences are respectively caused even after the offset cancellation is applied, which results in the amplitude difference deviation. That is, the conventional method has a system constitution in which the amplitude difference deviation is intrinsically caused, which makes it impossible to expect the amplitude difference deviation characteristic to be improved to some extent or more. Therefore, the amplitude difference deviation is increased to cause a problem that vertical stripes are generated in the LCD display.
Further, the conventional operational-amplifier is not capable of coping with the driving method referred to as 2H inversion driving. The 2H inversion driving is a method for continuously driving the positive side voltage or the negative side voltage during two horizontal periods. FIG. 9 shows the output drive of the 2H inversion driving method.
The operational amplifier shown in FIG. 6 has at most only a current discharging capability for the current source I102, and the operational amplifier shown in FIG. 7 has at most only a current sucking capability for the current source I202. When the current discharging capability and the current sucking capability can be obtained at most only for the current source I102 and I202, the conventional operational amplifier is unable to cope with the 2H inversion driving method. Note that depending upon the size of the N-channel MOS transistor MN3 and the P-channel MOS transistor MP203, the current sucking capability of the operational amplifier shown in FIG. 6 and the current discharging capability of the amplifier shown in FIG. 7 can be increased to a certain level.
The reason why the 2H inversion driving method cannot be coped with when the drive current discharging capability of the operational amplifier shown in FIG. 6 and the current sucking capability of the operational amplifier shown in FIG. 7 are small, is that there arises no problem because the operational amplifier in FIG. 7 performs a current discharging operation in the rising waveform of 1H, but when the voltage of the second H is lower than the voltage of the first H, the operation to suck the drive current is performed to cause the drive current to be insufficient.